28 lines
1.7 KiB
Markdown
28 lines
1.7 KiB
Markdown
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# A Performance Analysis of High-Level Synthesis for FPGAs
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This repository stores the code and latex of my bachelor's thesis. The full thesis PDF can be found in [hls_performance_thesis.pdf](hls_performance_thesis.pdf).
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## Abstract
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It is becoming increasingly popular to use Field-Programmable Gate Arrays (FPGAs)
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as hardware accelerators in order to speed up certain parts of an algorithm. FPGAs
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promise more energy efficiency and increased performance compared to CPUs. They are,
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however, traditionally programmed with Hardware Description Languages (HDLs), which
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are notoriously hard to use.
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To accelerate their adoption in different contexts and domains, FPGAs can nowadays
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also be programmed with high-level languages, such as C/C++ or OpenCL, in a process
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called High-Level Synthesis (HLS). However, it can be a challenge to efficiently accelerate
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algorithms using HLS.
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In this thesis, we investigate the performance of HLS for a non-trivial case-study. To
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this end, we devise a performance comparison between a sequential CPU algorithm and its
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FPGA version, programmed with OpenCL for the Xilinx Vitis platform. Our case study is a
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string-searching algorithm using the FM-index method, which is able to efficiently locate
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substrings in arbitrarily long texts.
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Our naive reference implementation is a simple port from CPU to OpenCL. In search
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for more performance, on top of this naive OpenCL implementation, we also propose and
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evaluate two FPGA-specific optimizations, suggested by literature.
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Our empirical analysis shows that optimizations can greatly improve the performance of
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algorithms programmed with HLS for FPGAs. However, the performance of our HLS-based
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FPGA version for our case study could not match the performance of the CPU, despite
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being more work efficient.
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