hls-performance-thesis/code/fpga/ndrange.cfg

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2021-07-03 15:59:32 +00:00
platform=xilinx_u250_gen3x16_xdma_3_1_202020_1
debug=1
save-temps=1
[connectivity]
nk=fmindex:5
sp=fmindex_1.bwt:DDR[1]
sp=fmindex_1.alphabet:DDR[2]
sp=fmindex_1.ranks:DDR[3]
sp=fmindex_1.sa:DDR[2]
sp=fmindex_1.ranges:DDR[2]
sp=fmindex_1.out:DDR[1]
sp=fmindex_2.bwt:DDR[1]
sp=fmindex_2.alphabet:DDR[2]
sp=fmindex_2.ranks:DDR[3]
sp=fmindex_2.sa:DDR[2]
sp=fmindex_2.ranges:DDR[2]
sp=fmindex_2.out:DDR[1]
sp=fmindex_3.bwt:DDR[1]
sp=fmindex_3.alphabet:DDR[2]
sp=fmindex_3.ranks:DDR[3]
sp=fmindex_3.sa:DDR[2]
sp=fmindex_3.ranges:DDR[2]
sp=fmindex_3.out:DDR[1]
sp=fmindex_4.bwt:DDR[1]
sp=fmindex_4.alphabet:DDR[2]
sp=fmindex_4.ranks:DDR[3]
sp=fmindex_4.sa:DDR[2]
sp=fmindex_4.ranges:DDR[2]
sp=fmindex_4.out:DDR[1]
sp=fmindex_5.bwt:DDR[1]
sp=fmindex_5.alphabet:DDR[2]
sp=fmindex_5.ranks:DDR[3]
sp=fmindex_5.sa:DDR[2]
sp=fmindex_5.ranges:DDR[2]
sp=fmindex_5.out:DDR[1]
[profile]
data=all:all:all